8250 UART

                 Universal Asynchronous Receiver/Transmitter                  

                       Port assignments and meanings:

       Port 3F8 Transmit/Receive Buffer or Divisor Latch LSB
                (baud rate divisor LSB) if bit 7 of port 3FB is set

       Port 3F9 Interrupt Enable Register (IER) or baud rate divisor
                MSB if bit 7 of port 3FB is set

Port 2F9, 3F9
Bit	Dec	Hex	Description
0	1	01h	1 = enable data available int.
1	2	02h	1 = enable (THRE) interrupt
2	4	04h	1 = enable lines status int.
3	8	08h	1 = enable modem-status-change int.
4	16	10h	forced to zero
5	32	20h
6	64	40h
7	128	80h

       Port 3FA Interrupt Identification Register (IIR, prioritized)

Port 2FA, 3FA
Bit	Dec	Hex	Description
0	1	01h	1 = no int. pending, 0=int. pending
1	2	02h	Interrupt ID bits (see below)
2	4	04h	Interrupt ID bits (see below)
3	8	08h	forced to zero
4	16	10h
5	32	20h
6	64	40h
7	128	80h

        ID
       Bits Meaning                 Priority     To reset
        00  modem-status-change      lowest      read MSR
        01  transmit-register-empty  low         read IIR / write THR
        10  data-available           high        read rec buffer reg
        11  line-status              highest     read LSR

       - interrupt pending flag uses reverse logic, 0 = pending, 1 = none
       - interrupt will occur if any of the line status bits are set
       - THRE bit is set when THRE register is emptied into the TSR

                    Port 3FB Line Control Register (LCR)

Port 2FB, 3FB
Bit	Dec	Hex	Description
0	1	01h	word length select bits (see below)
1	2	02h	word length select bits (see below)
2	4	04h	0 = 1 stop bit, 1=1.5 or 2 bits
3	8	08h	0 = no parity, 1 = parity (PEN)
4	16	10h	0 = odd parity, 1 = even (EPS)
5	32	20h	0 = parity disabled, 1 = enabled
6	64	40h	0 = break disabled, 1 = enabled
7	128	80h	1 = addr baud rate divisor (DLAB)

       Word length bits:

             00 = 5 bits per character
             01 = 6 bits per character
             10 = 7  bits per character
             11 = 8 bits per character

                   Port 3FC Modem Control Register (MCR)

Port 2FC, 3FC
Bit	Dec	Hex	Description
0	1	01h	1 = activate DTR
1	2	02h	1 = activate RTS
2	4	04h	OUT1
3	8	08h	OUT2
4	16	10h	0 = normal, 1 = loop back test
5	32	20h	forced to zero
6	64	40h
7	128	80h

                    Port 3FD Line Status Register (LSR)

Port 2FD, 3FD
Bit	Dec	Hex	Description
0	1	01h	1 = data ready
1	2	02h	1 = overrun error (OR)
2	4	04h	1 = parity error (PE)
3	8	08h	1 = framing error (FE)
4	16	10h	1 = break interrupt (BI)
5	32	20h	1 = trans. hold reg. empty (THRE)
6	64	40h	1 = trans. shift reg. empty (TSRE)
7	128	80h	forced to zero

                    Port 3FE Modem Status Register (MSR)

Port 2FE, 3FE
Bit	Dec	Hex	Description
0	1	01h	1 = CTS changed state
1	2	02h	1 = DSR changed state
2	4	04h	1 = Ring Indicator changed state
3	8	08h	1 = rec. line signal detect chg state
4	16	10h	1 = CTS
5	32	20h	1 = DSR
6	64	40h	1 = ring indicator (RI)
7	128	80h	1 = receive line signal detect

                  Port 3FF Scratch Pad Register (2FF also)

       - 8250s, 16450s and 16550s are programmed identically
       - PCs are capable of 38.4Kb, while ATs are capable of 115.2Kb
       - see  INT TABLE  for IRQ interrupt assignments
       - see  PORTS  for COMx port assignment (3F8,2F8,3E8,2E8,3220...)
       - may lose THRE interrupt if THRE and RD/LS int occur simultaneously
       - data loss can occur w/o overrun/framing errors if serviced to slow