8253 PIT
Home Up Feedback Contents Search

                    8253 Programmable Interval Timer (PIT)                    

       Port 40h, 8253 Counter 0 divisor (mode 3)
       Port 41h, 8253 Counter 1 RAM refresh counter (mode 2)
       Port 42h, 8253 Counter 2 Cassette and Speaker functions
       Port 43h, 8253 Mode control, data format:
Mode Control
Bit Dec Hex  Description
0 1 01h  0 binary counter decrementing
 1 BCD counter decrementing
1 2 02h  000 mode 0, countdown with optional inhibit (level output)
 001 mode 1, countdown with optional restart (level output)
 010 mode 2, generate one pulse out of N (used for DMA refresh)
 011 mode 3, generate square wave for channels 0 and 2
 100 mode 4, countdown with optional inhibit (pulse output)
 101 mode 5, countdown with optional restart (pulse output)
2 4 04h
3 8 08h
4 16 10h  00 latch present counter value
 01 read/write of MSB
 10 read/write of LSB
 11 read/write LSB, followed by write of MSB
5 32 20h
6 64 40h  00 select counter 0
 01 select counter 1
 10 select counter 2
7 128 80h
       Example code:

       timer_countdn  equ  7FFFh  ; approx 36 interrupts per second

       cli
       mov  al,00110110b     ; bit 7,6 = (00) timer counter 0
                             ; bit 5,4 = (11) write LSB then MSB
                             ; bit 3-1 = (011) generate square wave
                             ; bit 0 = (0) binary counter
       out  43h,al           ; prep PIT, counter 0, square wave&init count
       mov  cx,timer_countdn ; default is 0xFFFF (18.2 times per second)
                             ; interrupts when counter decrements to 0
       mov  al,cl            ; send LSB of timer count
       out  40h,al
       mov  al,ch            ; send MSB of timer count
       out  40h,al
       sti


Copyright © 1985 to 2022 Beta Systems                            Last modified: Wednesday, January 05, 2022 .