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8259 Programmable Interrupt Controller (PC relative)
| ICR
Interrupt Command Register Port 20h, A0h |
| Bit |
Dec |
Hex |
Description |
| 0 |
1 |
01h |
interrupt
request level (0-7, specific EOI) |
| 1 |
2 |
02h |
| 2 |
4 |
04h |
| 3 |
8 |
08h |
not used
(0) |
| 4 |
16 |
10h |
| 5 |
32 |
20h |
EOI type
(see table) |
| 6 |
64 |
40h |
| 7 |
128 |
80h |
Bits 7-5 specify End Of Interrupt (EOI) type: (PC specific)
001 non-specific EOI command
010 NOP
011 specific EOI command
110 set priority command (uses bits 2-0)
| IMR
Interrupt Mask Register Port 21h, A1h |
| Bit |
Dec |
Hex |
Description |
| 0 |
1 |
01h |
0 = service
IRQ0, 1 = mask off |
| 1 |
2 |
02h |
0 = service
IRQ1, 1 = mask off |
| 2 |
4 |
04h |
0 = service
IRQ2, 1 = mask off |
| 3 |
8 |
08h |
0 = service
IRQ3, 1 = mask off |
| 4 |
16 |
10h |
0 = service
IRQ4, 1 = mask off |
| 5 |
32 |
20h |
0 = service
IRQ5, 1 = mask off |
| 6 |
64 |
40h |
0 = service
IRQ6, 1 = mask off |
| 7 |
128 |
80h |
0 = service
IRQ7, 1 = mask off |
Internal registers
IRR - Interrupt Request Register, maintains a bit vector indicating
which IRQ hardware events are awaiting service
ISR - In Service Register, tracks IRQ line currently being serviced
Hardware Interrupt Sequence of Events:
1. 8259 IRQ signal is raised high by hardware setting the
corresponding IRR bits true.
2. PIC evalutates the interrupt requests and signals the CPU
where appropriate.
3. CPU acknowleges the INT by pulsing INTA (inverted)
4. INTA signal from CPU is received by the PIC, which then sets the
highest priority ISR bit, and clears the corresponding IRR bit
5. CPU sends a second INTA pulse which causes the PIC to send the
interrupt ID byte onto the bus. CPU begins interrupt proccesing.
6. Interrupts of lower and equal priority are blocked until a
Non-Specific EOI (20h) is sent to command port.
8259 Programmable Interrupt Controller Notes
* PCs operate in fully nested mode, where a Non-Specific EOI resets
the interrupt identified by the highest bit value in the ISR
* 8259s can be chained together where the INT pin (output) of a
slave 8259 can be used as the input to an IRQ line allowing up
to 64 priority vectored interrupts. The AT uses two 8259s for
a total of 16 hardware interrupt levels
* The first 8259 ports are located at 20h (command) and 21h (mask)
* The second 8259 ports are located at A0h (command) and A1h (mask)
* PC and AT interrupts are Edge Triggered while PS/2s are Level
Sensitive
* Some ASIC chips designed for Tandy 1000 Systems malfunction if
specific and non-specific EOIs are mixed
* For a more indepth discussion of the 8259, see Intel's "Micro-
processor and Peripherals Handbook, Volume I" |
