|
| |
Rotate Right
|
86/88 |
Y |
186 |
Y |
286 |
Y |
386 |
Y |
486 |
Y |
ROR destination, count |
|
Ovfl |
Y |
Dir |
N |
Int |
N |
Trap |
N |
Sign |
N |
Zero |
N |
Aux |
N |
Prty |
N |
Carry |
Y |
+--------------------+
| |
+->> Destination --+-> CF
ROR shifts the word or byte at the destination to the right by the
number of bit positions specified in the second operand, COUNT. As
bits are transferred out the right (low-order) end of the destination,
they re-enter on the left (high-order) end. The Carry Flag is updated
to match the last bit shifted out of the right end.
If COUNT is not equal to 1, the Overflow flag is undefined. If COUNT
is equal to 1, the Overflow Flag is set to the XOR of the top 2 bits
of the result.
Notes: COUNT is normally taken as the value in CL. If,
however, you wish to rotate by only one position,
replace the second operand, CL, with the value 1, as
shown in the first example above.
The 80286 and 80386 microprocessors limit the COUNT
value to 31. If the COUNT is greater than 31, these
microprocessors use COUNT MOD 32 to produce a new
COUNT between 0 and 31. This upper bound exists to
limit the amount of time an interrupt response will
be delayed waiting for the instruction to complete.
Multiple RORs that use 1 as the COUNT may be faster
and require less memory than a single ROR that uses
CL for COUNT.
The overflow flag is undefined when the rotate count
is greater than 1.
------------------------------------ Timing ----------------------------------
OpCode Instruction 386 286 86
D0/1 ROR r/m8,1 9/10 2/7 2/15+EA
D2/1 ROR r/m8,CL 9/10 5/8 8/20+4/bit
C0/1 ib ROR r/m8,imm8 9/10 5/8
D1/1 ROR r/m16,1 9/10 2/7 2/15+EA
D3/1 ROR r/m16,CL 9/10 5/8 8/20+4/bit
C1/1 ib ROR r/m16,imm8 9/10 5/8
D1/1 ROR r/m32,1 9/10
D3/1 ROR r/m32,CL 9/10
C1/1 ib ROR r/m32,imm8 9/10
See Also RCR ROL RCL SAR SAL SHL SHR Flags |