|
| |
Shift Arithmetic Left
|
86/88 |
Y |
186 |
Y |
286 |
Y |
386 |
Y |
486 |
Y |
SAL destination, count |
|
Ovfl |
Y |
Dir |
N |
Int |
N |
Trap |
N |
Sign |
Y |
Zero |
Y |
Aux |
? |
Prty |
Y |
Carry |
Y |
CF <<-- Destination <<-- 0
SAL shifts the word or byte at the destination to the left by the
number of bit positions specified in the second operand, COUNT. As
bits are transferred out the left (high-order) end of the destination,
zeroes are shifted in the right (low-order) end. The Carry Flag is
updated to match the last bit shifted out of the left end.
If COUNT is not equal to 1, the Overflow flag is undefined. If COUNT
is equal to 1, the Overflow Flag is cleared if the top 2 bits of the
original operand were the same, otherwise the Overflow Flag is set.
Notes: COUNT is normally taken as the value in CL. If,
however, you wish to shift only one position,
replace the second operand, CL, with the value 1, as
shown in the first example above.
The 80286 and 80386 microprocessors limit the COUNT
value to 31. If the COUNT is greater than 31, these
microprocessors use COUNT MOD 32 to produce a new
COUNT between 0 and 31. This upper bound exists to
limit the amount of time an interrupt response will
be delayed waiting for the instruction to complete.
Multiple SALs that use 1 as the COUNT may be faster
and require less memory than a single SAL that uses
CL for COUNT.
SHL, Shift Logical Left, is the same instruction;
SHL is a synonym for SAL.
The overflow flag is undefined when the shift count
is greater than 1.
------------------------------------ Timing ----------------------------------
OpCode Instruction 386 286 86
D0/4 SAL r/m8,1 9/10 2/7 2/15+EA
D2/4 SAL r/m8,CL 9/10 5/8 8/20+4/bit
C0/4 ib SAL r/m8,imm8 9/10 5/8
D1/4 SAL r/m16,1 9/10 2/7 2/15+EA
D3/4 SAL r/m16,CL 9/10 5/8 8/20+4/bit
C1/4 ib SAL r/m16,imm8 9/10 5/8
D1/4 SAL r/m32,1 9/10
D3/4 SAL r/m32,CL 9/10
C1/4 ib SAL r/m32,imm8 9/10
See Also SHL SAR SHR RCL RCR ROL ROR Flags |