|
| |
Shift Right
|
86/88 |
Y |
186 |
Y |
286 |
Y |
386 |
Y |
486 |
Y |
SHR/SHRD destination, count |
|
Ovfl |
Y |
Dir |
N |
Int |
N |
Trap |
N |
Sign |
Y |
Zero |
Y |
Aux |
? |
Prty |
Y |
Carry |
Y |
0 -->> Destination -->> CF
SAR shifts the bits in destination to the right by the number of
positions specified in the count operand (or in CL, if no count
operand is included). 0s are shifted in on the left. If the sign bit
retains its original value, the Overflow Flag is cleared; it is set if
the sign changes. The Carry Flag is updated to reflect the last bit
shifted.
If COUNT is not equal to 1, the Overflow flag is undefined, otherwise
the Overflow Flag is set to the high-order bit of the original
operand.
Notes: COUNT is normally taken as the value in CL. If,
however, you wish to shift only one position,
replace the second operand, CL, with the value 1, as
shown in the first example below.
The 80286 and 80386 microprocessors limit the COUNT
value to 31. If the COUNT is greater than 31, these
microprocessors use COUNT MOD 32 to produce a new
COUNT between 0 and 31. This upper bound exists to
limit the amount of time an interrupt response will
be delayed waiting for the instruction to complete.
Multiple SHRs that use 1 as the COUNT may be faster
and require less memory than a single SHR that uses
CL for COUNT.
The overflow flag is undefined when the shift count
is greater than 1.
------------------------------------ Timing ----------------------------------
OpCode Instruction 386 286 86
D0/5 SHR r/m8,1 9/10 2/7 2/15+EA
D2/5 SHR r/m8,CL 9/10 5/8 8/20+4/bit
C0/5 ib SHR r/m8,imm8 9/10 5/8
D1/5 SHR r/m16,1 9/10 2/7 2/15+EA
D3/5 SHR r/m16,CL 9/10 5/8 8/20+4/bit
C1/5 ib SHR r/m16,imm8 9/10 5/8
D1/5 SHR r/m32,1 9/10
D3/5 SHR r/m32,CL 9/10
C1/5 ib SHR r/m32,imm8 9/10
0F AC SHRD r/m16, r16, imm8 3/7
0F AC SHRD r/m32, r32, imm8 3/7
0F AD SHRD r/m16, r16, CL 3/7
0F AD SHRD r/m32, r32, CL 3/7
See Also SAR SHL SAL RCR RCL ROR ROL Flags |