|
| |
Shift Arithmetic Right
|
86/88 |
Y |
186 |
Y |
286 |
Y |
386 |
Y |
486 |
Y |
SAR destination, count |
|
Ovfl |
Y |
Dir |
N |
Int |
N |
Trap |
N |
Sign |
Y |
Zero |
Y |
Aux |
? |
Prty |
Y |
Carry |
Y |
SF -->> Destination -->> CF
SAR shifts the word or byte in destination to the right by the number
of bit positions specified in the second operand, COUNT. As bits are
transferred out the right (low-order) end of the destination, bits
equal to the original sign bit are shifted into the left (high-order)
end, thereby preserving the sign bit. The Carry Flag is set equal to
the last bit shifted out of the right end.
If COUNT is not equal to 1, the Overflow flag is undefined. If COUNT
is equal to 1, the Overflow flag is cleared.
Notes: COUNT is normally taken as the value in CL. If,
however, you wish to shift only one position,
replace the second operand, CL, with the value 1, as
shown in the first example above.
The 80286 and 80386 microprocessors limit the COUNT
value to 31. If the COUNT is greater than 31, these
microprocessors use COUNT MOD 32 to produce a new
COUNT between 0 and 31. This upper bound exists to
limit the amount of time an interrupt response will
be delayed waiting for the instruction to complete.
Multiple SARs that use 1 as the COUNT may be faster
and require less memory than a single SAR that uses
CL for COUNT.
The overflow flag is undefined when the shift count
is greater than 1.
------------------------------------ Timing ----------------------------------
OpCode Instruction 386 286 86
D0/7 SAR r/m8,1 9/10 2/7 2/15+EA
D2/7 SAR r/m8,CL 9/10 5/8 8/20+4/bit
C0/7 ib SAR r/m8,imm8 9/10 5/8
D1/7 SAR r/m16,1 9/10 2/7 2/15+EA
D3/7 SAR r/m16,CL 9/10 5/8 8/20+4/bit
C1/7 ib SAR r/m16,imm8 9/10 5/8
D1/7 SAR r/m32,1 9/10
D3/7 SAR r/m32,CL 9/10
C1/7 ib SAR r/m32,imm8 9/10
See Also SHR SAL SHL RCR RCL ROR ROL Flags |